View LC88F40F0PAU_3173146.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. d1510hkpc 20101005-s00001, s00002, s00003, s00004, s00005, s00006 no.a1853-1/32 * this product is licensed from silicon storage tec hnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. ver.1.23 lc88f40h0pa/pau lc88f40f0pa /pau lc88f40d0pa/pau overview the lc88f40h0pa/pau, lc88f40f0pa/pau and lc88f40d0pa/pau are 16-bit microcontrollers which are ideally suited as a system controller in car audio applications for the control of ?mp3 and wma and other compression decoders through cd/usb,? ?cd mechan isms and cd dsps,? ?displays,? and ?dsp tuners.? they are configured around a cpu that operates at a high speed, and incorporat e an internal flash rom (all flash, onboard programmable) and ram. these 16-bit microcontrollers integrate on a single chip such principal functions as on-chip debugging, 16-bit timer/counter (may be divided into 8-bit timers/counters), synchronous sio (also used as the i 2 c bus interface), uart (full duplex), 12-bit pwm, 12-bit resolution (8-bit resolution selectable) 13-channel a/d converter, and 16 vector interrupts. microcontroller model line-up (list of rom and ram sizes) type no. flash rom (byte) ram (byte) lc88f40h0pa/pau 512k 30k lc88f40f0pa/pau 384k 20k lc88f40d0pa/pau 256k 12k features power supply voltage ? main power supply voltage (v dd cpu) 3.3v 0.3v ? i/o power supply (v dd port) v dd cpu to 5.5v cmos lsi for car audio systems 16-bit etr microcontroller (all flash) orderin g numbe r : ena1853a
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-2/32 flash rom (all flash) ? single 3.3v power supply, on-board writeable ? block erase in 512 byte units minimum instruction cycle time (tcyc) ? 83.3ns ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1 bit units : 86 (p0n, p1n, p2n, p3n, p4n, p5n, p6n, p7n pan, pb0 to pb6, pc0, pd0 to pd5) ? dedicated pin for low-pass filter connection : 1 (lpfo) ? regulator pins : 1 (vreg) ? reset pins : 1 (resb) ? test pins : 1 (test) ? dedicated pins for crystal oscillator : 2 (xt1, xt2) ? power pins : 2 (v dd cpu, v ss 1: main power, i/o power supply) : 4 (v dd port1 to 2, v ss 2 to 3: i/o power supply) : 2 (v dd pll, v ss 4: pllvco power) sio: 6 channels (4 channels are also used as i 2 c bus.) ? sio0: 8 bit synchronous sio 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (4 to 512 transfer clock cycle) 3) automatic and continuous data transfer fu nction to and from the ram (max. 4096 bytes) ? sio1: 8 bit synchronous sio 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (4 to 512 transfer clock cycle) 3) automatic and continuous data transfer fu nction to and from the ram (max. 4096 bytes) ? smiic0: single master i 2 c/8-bit synchronous sio mode 0: single-master mode communication mode 1: synchronous 8-bit serial i/o (msb first) ? smiic1: single master i 2 c/8-bit synchronous sio mode 0: single-master mode communication mode 1: synchronous 8-bit serial i/o (msb first) ? smiic2: single master i 2 c/8-bit synchronous sio mode 0: single-master mode communication mode 1: synchronous 8-bit serial i/o (msb first) ? smiic3: single master i 2 c/8-bit synchronous sio mode 0: single-master mode communication mode 1: synchronous 8-bit serial i/o (msb first) uart: 4 channels 1) data length : 8 bits (lsb first) 2) stop bits : 1 bit 3) parity bits : none/even parity/odd parity 4) transfer rate : 8 to 4096 cycle 5) baudrate source clock : system clock/xt clock/vco clock 5) wakeup function 6) full duplex communication
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-3/32 timers ? timer 0: 16-bit timer that supports pwm/toggle outputs 1) 5-bit prescaler 2) 8-bit pwm 2, 8-bit timer + 8-bit pwm mode selectable 3) clock source selectable from system clock, xt clock, vco clock, and internal rc oscillator ? timer 1: 16-bit timer with capture registers 1) 5-bit prescaler 2) may be divided into 2 channels of 8-bit timer 3) clock source selectable from system clock, xt clock, vco clock, and internal rc oscillator ? timer 2: 16-bit timer with capture registers 1) 4-bit prescaler 2) may be divided into 2 channels of 8-bit timer 3) clock source selectable from system clock, xt clock, vco clock, and external events ? timer 3: 16-bit timer that supports pwm/toggle outputs 1) 8-bit prescaler 2) 8-bit pwm 2ch or 8-bit timer + 8-bit pwm mode selectable 3) clock source selectable from system clock, xt clock, vco clock, and external events ? timer 4: 16-bit timer that supports toggle outputs 1) clock source selectable from system clock and prescaler 0 ? timer 5: 16-bit timer that supports toggle outputs 1) clock source selectable from system clock and prescaler 0 ? timer 6: 16-bit timer that supports toggle outputs 1) clock source selectable from system clock and prescaler 1 ? timer 7: 16-bit timer that supports toggle outputs 1) clock source selectable from system clock and prescaler 1 * prescaler 0 and 1 are consisted of 4 bits and can ch oose their clock source from xt clock or vco clock. ? timer 8 1) clock source may be selected from xt clock (32.768khz) and frequency-divided output of clock. 2) interrupts can be generated in 8 timing schemes. ? watch timer 1) clock may be selected from xt clock (32.768khz) 2) interrupts can be generated in 4 timing schemes. day, minute and second counters 1) count-up of clocks output from watch timer 2) configured with day counter, minute counter, second counter 3) continues operation when in holdx mode. ad converter 1) 12/8 bits resolution selectable 2) analog input: 13 channels 3) comparator mode 4) automatic reference voltage generation
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-4/32 pwm: multifrequency 12-bit pwm 4 channels ? pwm0: multifrequency 12-bit pwm 2 channels (pwm0a and pwm0b) ? pwm1: multifrequency 12-bit pwm 2 channels (pwm1a and pwm1b) 1) 2-channel pairs controlled independently of one another 2) clock source selectable from system clock or vco clock 3) 8-bit prescaler: tpwmr0 = (prescaler value + 1) clock period 4) 8-bit fundamental wave pwm generator circuit + 4-bit additional pulse generator circuit 5) fundamental wave pwm mode fundamental wave period : 16 tpwmr0 to 256 tpwr0 high pulse width : 0 to (fundamental wave period - tpwmr0) 6) fundamental wave + additional pulse mode fundamental wave period : 16 tpwr0 to 256 tpwr0 overall period : fundamental wave period 16 high pulse width : 0 to (overall period - tpwr0) watchdog timer: 1 channel ? driven by the timer 8 + internal watchdog timer dedicated counter ? interrupt or reset mode selectable interrupts ? 63 sources, 16 vector addresses 1) provides three levels of multiplex interrupt control. any interrupt requests of the leve l equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address interrupt source 1 08000h wdt (1) 2 08004h timer 8 (2)/watch timer (1) 3 08008h timer 0 (2) 4 0800ch int0 (1) 5 08010h 6 08014h int1 (1) 7 08018h int2 (1)/timer 1 (2)/uart 2 (3) 8 0801ch int3 (1)/timer 2 (3)/smiic0 (1) 9 08020h int4 (1)/timer 3 (2)/smiic1 (1)/ir remote control receive (4) 10 08024h int5 (1)/timer 4 (1)/sio1 (2) 11 08028h 12 0802ch pwm0 (1)/pwm1 (1)/smiic2 (1) 13 08030h adc (1)/timer 5 (1)/smiic3 (1) 14 08034h int6 (1)/timer 6 (1)/uart 3 (3) 15 08038h int7 (1)/timer 7 (1)/sio0 (2)/uart 4 (3) 16 0803ch port 0 (3)/port 5 (8)/uart 5 (3) ? 3 priority levels selectable. ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? a number enclosed in parenthese s denotes the number of sources. subroutine stack: entire maxi mum ram space (the stack is allocated in ram.) ? subroutine calls that automatically save psw, interrupt vector calls: 6 bytes ? subroutine calls that do not automatically save psw: 4 bytes high-speed multiplication/division instructions ? 16 bits 16 bits ? 16 bits 16 bits ? 32 bits 16 bits
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-5/32 infrared remote controller receive functions 1) noise rejection function 2) ppm(pulse position modulation), compatible with manchester and other data encoding systems. 3) holdx mode release function oscillation circuits ? rc oscillator circuit (internal): for system clock ? xt oscillator circuit: for system clock ? vco oscillator circuit (internal): for system clock low power consumption ? halt mode: halts instruction execution while allowi ng the peripheral circuits to continue operation. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. ? holdx mode: suspends instruction execution and operation of all the peripheral circuits except the modules run on the xt clock. system clock divider function ? can run on low current. ? 1/1 to 1/128 of the system clock frequency can be set.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-6/32 standby function ? halt mode: halts instruction execution while allowi ng the peripheral circuits to continue operation. 1) both the xt oscillator and internal rc oscillator retain the state established when the standby mode is entered. 2) both the xt and vco clocks retain the state established when the standby mode is entered. 3) there are the two ways of releasing the halt mode. (1) generating a reset condition (2) generating an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) both the xt oscillator and internal rc oscillator automatically stop operation. 2) xt clock and vco clock oscillators automatically stop. 3) there are the six ways of releasing the hold mode. (1) generating a reset condition (2) setting at least one of the int0, int1, int2, int4 , int5, int6, and int7 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established at port 5 (5) having an interrupt request generated in uart2, uart3, uart4, or uart5 (6) having an interrupt reques t generated in sio0 or sio1 ? holdx mode: suspends instruction execution and operation of all the peripheral circuits except the modules run on the xt clock. 1) the internal rc oscillator automatically stops operation. 2) the xt clock retains the state established when the holdx mode is entered and the vco clock automatically stops. 3) there are nine ways of resetting the holdx mode. (1) generating a reset condition (2) setting at least one of the int0, int1, int2, int4 , int5, int6, and int7 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established at port 5 (5) having an interrupt request generated in uart2, uart3, uart4, or uart5 (6) having an interrupt reques t generated in sio0 or sio1 (7) having an interrupt source established in the timer 8 circuit (8) having an interrupt source established in the infrared remote controller receive circuit (9) having an interrupt source established in the clock timer circuit reset ? external reset ? voltage drop detection type of reset circuit (vdet circuit) incorporated 1) normal mode detection voltage: 2.85v 0.15v 2) hold mode detection voltage: 1.42v 0.15v on-chip debugger function ? supports software debugging with the ic mounted on the target board. ? supports source line debugging and tracing functions, and breakpoint setting and real time monitor. ? single-wire communication shipping form ? qip100e (lead free product)
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-7/32 package dimensions unit : mm (typ) 3151a sanyo : qip100e(14x20) 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0.1 0.3 0.65 (0.58) 130 80 51 31 50 100 81
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-8/32 pin assignment top view 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pa0/sm1ck pa1/sm1da pa2/sm1do pa3/sm2ck pa4/sm2da pa5/sm2do pa6/u5rx pa7/u5tx pb0/pwm10 pb1/pwm11 pb2 pb3 pb4 pb5/int7 pb6 v dd pll v ss 4 lpfo p50/p5int0 p51/p5int1 p52/p5int2 p53/p5int3 p54/p5int4 p55/p5int5 p56/p5int6 p57/p5int7 test resb pc0 vreg v ss 1 xt1 xt2 v dd cpu p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 p70/an8 p71/an9 p72/an10 p73/an11 p74/an12 p75/sm3ck p76/sm3da p77/sm3do p44/sio1 p45/sck1 p46/pwm00 p47/pwm01 v ss 2 v dd port1 p27/rmin p26/t5o p25/t4o p24/sm0do p23/sm0da p22/sm0ck p21/int5 p20/int4 pd5 pd4 pd3 pd2 pd1/u4tx pd0/u4rx v ss 3 v dd port2 p37/t7o p36/t6o p35/u3tx p34/u3rx p33/int3 p32/int2 p31/int1 p30/int0 p17/u2tx p16/u2rx p15/t3outh p14/t3outl p13 p12/sck0 p11/sio0 p10/so0 p07/t0pwmh p06/t0pwml p05/p05int p04/p04int p03/p0int p02/p0int p01/p0int p00/p0int p40/int6 p41 p42 p43/so1 lc88f40h0pa/pau lc88f40f0pa/pau lc88f40d0pa/pau
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-9/32 system block diagram clock generator rc x?tal port 0 port 1 sio0 sio1 smiic0 timer 0 timer 1 timer 2 timer 3 port 2 port 3 port 4 port 6 smiic1 port b timer 4 smiic3 on-chip debugger port 7 cpu ram flash rom timer 8 watchdog timer uart2 port c port d timer 7 port a smiic2 timer 5 timer 6 uart4 uart5 uart3 pwm1 pwm0 port 5 watch timer day, minute and second counter adc infrared remote controller receive int0 to int7
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-10/32 pin description name i/o description v dd cpu - + power sources 3.3v power supply (3.0 to 3.6v) v dd port1 - + power sources i/o power supply (v dd cpu to 5.5v) v dd port2 - + power sources i/o power supply (v dd cpu to 5.5v) v dd pll - + power sources pllvco power supply (3.0 to 3.6v) v ss 1 - - power sources v ss 2 - - power sources v ss 3 - - power sources v ss 4 - - power sources port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? port 0 interrupt input (p00 to p05) ? hold release input (p00 to p05) ? pin functions p06: timer 0l output p07: timer 0h output supply voltage from v dd port1 used (v dd cpu to 5.5v) port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p10: sio0 data output p11: sio0 data input/output p12: sio0 clock input/output p14: timer 3l output p15: timer 3h output p16: uart2 receive p17: uart2 transmit supply voltage from v dd port2 used (v dd cpu to 5.5v) port 2 p20 to p27 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p20: int4 input/hold release input/time r 3 event input/timer 2l capture input/ timer 2h capture input p21: int5 input/hold release input/time r 3 event input/timer 2l capture input/ timer 2h capture input p22: smiic0 clock input/output p23: smiic0 data bus input/output p24: smiic0 data (used in 3-wire sio mode) p25: timer 4 output p26: timer 5 output p27: remote control receive ? interrupt acknowledge type int4, int5: h level, l level, h edge, l edge, both edges supply voltage from v dd port1 used (v dd cpu to 5.5v) port 3 p30 to p37 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p30: int0 input/hold release input/timer 2l capture input p31: int1 input/hold release input/timer 2h capture input p32: int2 input/hold release input/time r 2 event input/timer 2l capture input p33: int3 input/hold release input/time r 2 event input/timer 2h capture input p34: uart3 receive p35: uart3 transmit p36: timer 6 output p37: timer 7 output ? interrupt acknowledge type int0 to int3: h level, l level, h edge, l edge, both edges supply voltage from v dd port2 used (v dd cpu to 5.5v) continued on next page.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-11/32 continued from preceding page. name i/o description port 4 p40 to p47 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p40: int6 input/hold release input p43: sio1 data output p44: sio1 data input/output p45: sio1 clock input/output p46: pwm00 output p47: pwm01 output ? interrupt acknowledge type int6: h level, l level, h edge, l edge, both edges supply voltage from v dd port1 used (v dd cpu to 5.5v) port 5 p50 to p57 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions ? port 5 interrupt function ? hold release input supply voltage from v dd cpu used (3.0 to 3.6v) port 6 p60 to p67 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions an0 (p60) to an7 (p67): ad converter input port supply voltage from v dd cpu used (3.0 to 3.6v) port 7 ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions an8 (p70) to an12 (p74): ad converter input port supply voltage from v dd cpu used (3.0 to 3.6v) p70 to p77 i/o p75: smiic3 clock input/output p76: smiic3 data bus input/output p77: smiic3 data (used in 3-wire sio mode) supply voltage from v dd port1 used (v dd cpu to 5.5v) port a pa0 to pa7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions pa0: smiic1 clock input/output pa1: smiic1 data bus input/output pa2: smiic1 data (used in 3-wire sio mode) pa3: smiic2 clock input/output pa4: smiic2 data bus input/output pa5: smiic2 data (used in 3-wire sio mode) pa6: uart5 receive pa7: uart5 transmit supply voltage from v dd port2 used (v dd cpu to 5.5v) port b pb0 to pb6 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions pb0: pwm10 output pb1: pwm11 output pb5: int7 input/hold release input ? interrupt acknowledge type int7: h level, l level, h edge, l edge, both edges supply voltage from v dd port2 used (v dd cpu to 5.5v) port c pc0 i/o ? 1-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units supply voltage from v dd cpu used (3.0 to 3.6v) port d pd0 to pd5 i/o ? 6-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions pd0: uart4 receive pd1: uart4 transmit supply voltage from v dd port1 used (v dd cpu to 5.5v) continued on next page.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-12/32 continued from preceding page. name i/o description xt1 i ? input terminal for 32.768khz x'tal oscillation xt2 o ? output terminal for 32.768khz x'tal oscillation resb i ? reset pin ? this must be set to low for 50 s or longer when the power is turned on and when a reset is required. test i/o ? test pin ? used to communicate with on-chip debugger ? 100k pull-down lpfo o ? lpf connection pin for pllvco vreg o ? regulator output pin connect a bypass capacitor to this pin
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-13/32 port output types the port output type and pull-up resistance must be set using the registers. the pin data can be read regardless of the i/o setting of the port. the port output type (cmos output or n-channel open drain output) and use/disuse of the pull-up resistor can be configured separately for each port. * make the following connection to minimize the noise input to the v dd cpu pin and prolong the backup time. be sure to electrically short the v ss 1, v ss 2, v ss 3 and v ss 4 pins. example 1: when data is being backed up in the hold mode, the h level signals to the output ports are fed by the backup capacitors. (v dd cpu = v dd port1 = v dd port2 = v dd pll) example 2: when data is being backed up in the hold mode, the h level output at any ports is not sustained and is unpredictable. (v dd cpu = v dd port1 = v dd port2 = v dd pll) power supply v ss 1 fo r buckup v ss 2v ss 3 v dd port2 v dd port1 v dd cpu lsi v dd pll v ss 4 vreg lpfo v ss 1 fo r buckup v ss 2v ss 3 v dd port2 v dd port1 v dd cpu lsi v dd pll v ss 4 vreg lpfo power supply
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-14/32 absolute maximum ratings at ta = 25 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin /remarks conditions min typ max unit v dd max(1) v dd cpu v dd pll v dd cpu=v dd port1 =v dd port2=v dd pll -0.3 +4.6 maximum supply voltage v dd max(2) v dd port1 v dd port2 v dd port1=v dd port2 -0.3 +6.5 input voltage v i (1) resb, xt1 -0.3 v dd (1)+0.3 v io (1) ports 5, 6 p70 to 74 ports c xt2 -0.3 v dd (1)+0.3 input/output voltage v io (2) ports 0, 1, 2, 3, 4 p75 to p77 ports a, b, d -0.3 v dd (2)+0.3 v ioph(1) ports 0, 1, 2, 3, 5 ports 6, 7, a, c, d p40 to p45 pb2 to pb6 cmos output selected per 1 application pin -10 peak output current ioph(2) p46, p47 pb0, pb1 per 1 application pin -20 iomh(1) ports 0, 1, 2, 3, 5 ports 6, 7, a, c, d p40 to p45 pb2 to pb6 cmos output selected per 1 application pin -7.5 average output current (note 1-1) iomh(2) p46, p47 pb0, pb1 per 1 application pin -10 ioah(1) ports 5 ports c total of all applicable pins -15 ioah(2) ports 6 p70 to p74 total of all applicable pins -15 ioah(3) ports 5, 6 p70 to p74 ports c total of all applicable pins -20 ioah(4) ports 2, d p75 to p77 total of all applicable pins -25 ioah(5) ports 0, 4 total of all applicable pins -25 ioah(6) ports 0, 2, 4, d p75 to p77 total of all applicable pins -45 ioah(7) ports 1, 3 total of all applicable pins -25 ioah(8) ports a, b total of all applicable pins -25 high level output current total output current ioah(9) ports 1, 3, a, b total of all applicable pins -45 ma note 1-1: average output current is av erage of current in 100ms interval. continued on next page.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-15/32 continued from preceding page. specification parameter symbol applicable pin /remarks conditions min typ max unit iopl(1) ports 0, 1, 3 ports 4, 5, 6 ports b, c, d p20, p21 p24 to p27 p70 to p74, p77 pa2, pa5 to pa7 per 1 application pin. 20 peak output current iopl(2) p22, p23 p75, p76 pa0, pa1 pa3, pa4 per 1 application pin. 25 ioml(1) ports 0, 1, 3 ports 4, 5, 6 ports b, c, d p20, p21 p24 to p27 p70 to p74, p77 pa2, pa5 to pa7 per 1 application pin. 10 average output current (note 1-1) ioml(2) p22, p23 p75, p76 pa0, pa1 pa3, pa4 per 1 application pin. 15 ioal(1) ports 5 ports c total of all applicable pins 15 ioal(2) ports 6 p70 to p74 total of all applicable pins 15 ioal(3) ports 5, 6 p70 to p74 ports c total of all applicable pins 20 ioal(4) ports 2, d p75 to p77 total of all applicable pins 25 ioal(5) ports 0, 4 total of all applicable pins 25 ioal(6) ports 0, 2, 4, d p75 to p77 total of all applicable pins 45 ioal(7) ports 1, 3 total of all applicable pins 25 ioal(8) ports a, b total of all applicable pins 25 low level output current total output current ioal(9) ports 1, 3, a, b total of all applicable pins 45 ma allowable power dissipation pd max qip100e ta = -40 to +85 c 400 mw operating temperature range topr -40 +85 c storage temperature range tstg -45 +125 c note 1-1: average output current is av erage of current in 100ms interval.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-16/32 allowable operating conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin /remarks conditions min typ max unit v dd (1) v dd cpu=v dd pll 3.0 3.6 operating supply voltage v dd (2) v dd port1 v dd port2 v dd (1) 5.5 memory sustaining supply voltage vhd v dd cpu=v dd port1 =v dd port2=v dd pll ram and register contents in hold mode. 1.2 v ih (1) ports 0, 1, 2, 3, 4 p75 to p77 ports a, b, d v dd port=v dd (2) 0.3 v dd (2) +0.7 v dd (2) v ih (2) ports 5, 6, c p70 to p74 v dd cpu=v dd (1) 0.3 v dd (1) +0.7 v dd (1) v ih (3) resb v dd cpu=v dd (1) 0.75 v dd (1) v dd (1) high level input voltage v ih (4) p22, p23, p75, p76 pa0, pa1, pa3, pa4 i 2 c side v dd port=v dd (2) 0.7 v dd (2) v dd (2) v il (1) ports 0, 1, 2, 3, 4 p75 to p77 ports a, b, d v dd port=v dd (2) v ss 0.1 v dd (2) +0.4 v il (2) ports 5, 6, c p70 to p74 v dd cpu=v dd (1) v ss 0.1 v dd (1) +0.4 v il (3) resb v dd cpu=v dd (1) v ss 0.25 v dd (1) low level input voltage v il (4) p22, p23, p75, p76 pa0, pa1, pa3, pa4 i 2 c side v dd port=v dd (2) v ss 0.3 v dd (2) v instruction cycle time tcyc v dd cpu=v dd (1) 83.3 s supply voltage rise time tpup v dd cpu 1 100 ms fmrc internal rc oscillation 0.5 1.0 2.0 mhz oscillation frequency range fmx?tal xt1, xt2 32.768khz crystal oscillation. 32.768 khz
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-17/32 electrical characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3, 4 p75 to p77 ports a, b, d output disable pull-up resistor off v in =v dd (2) (including the off-leak current of the output tr.) v dd port= v dd (1) to 5.5 1 i ih (2) ports 5, 6, c p70 to p74 resb output disable pull-up resistor off v in =v dd (1) (including the off-leak current of the output tr.) v dd cpu= 3.0 to 3.6 1 high level input current i ih (3) xt1 v in =v dd (1) v dd cpu= 3.0 to 3.6 0.18 i il (1) ports 0, 1, 2, 3, 4 p75 to p77 ports a, b, d output disable pull-up resistor off v in =v ss (including the off-leak current of the output tr.) v dd port= v dd (1) to 5.5 -1 i il (2) ports 5, 6, c p70 to p74 resb output disable pull-up resistor off v in =v ss (including the off-leak current of the output tr.) v dd cpu= 3.0 to 3.6 -1 low level input current i il (3) xt1 v in =v ss v dd cpu= 3.0 to 3.6 -0.18 a v oh (1) i oh =-1.0ma, v dd (2) v dd port= 4.5 to 5.5 v dd (2) -1.0 v oh (2) ports 0, 1, 2, 3 p40 to p45 p75 to p77 ports a, d pb2 to pb6 i oh =-0.4ma, v dd (2) v dd port= v dd (1) to 5.5 v dd (2) -0.4 v oh (3) i oh =-1.0ma, v dd (1) v dd cpu= 3.0 to 3.6 v dd (1) -1.0 v oh (4) ports 5, 6, c p70 to p74 i oh =-0.4ma, v dd (1) v dd cpu= 3.0 to 3.6 v dd (1) -0.4 v oh (5) i oh =-10ma, v dd (2) v dd port= 4.5 to 5.5 v dd (2) -1.5 high level output voltage v oh (6) p46, p47 pb0, pb1 i oh =-1.6ma, v dd (2) v dd port= v dd (1) to 5.5 v dd (2) -0.4 v ol (1) i ol =10ma v dd port= 4.5 to 5.5 1.5 v ol (2) ports 0, 1, 3, 4 p20, p21 p24 to p27, p77 pa2, pa5 to pa7 ports b, d i ol =1.6ma v dd port= v dd (1) to 5.5 0.4 v ol (3) ports 5, 6, c p70 to p74 i ol =1.6ma v dd cpu= 3.0 to 3.6 0.4 v ol (4) i ol =11ma v dd port= 4.5 to 5.5 1.5 low level output voltage v ol (5) p22, p23 p75, p76 pa0, pa1 pa3, pa4 i ol =3.0ma v dd port= v dd (1) to 5.5 0.4 v rpu(1) v dd port= 4.5 to 5.5 15 35 80 rpu(2) ports 0, 1, 2, 3, 4 p75 to p77 ports a, b, d v oh =0.9v dd v dd port= v dd (1) to 5.5 15 35 150 pull-up resistor rpu(3) ports 5, 6, c p70 to p74 v dd cpu= 3.0 to 3.6 15 35 150 k hysteresis voltage vhys resb ports 1, 2, 3, 4, 5 ports 7, a, b, c, d ports 1 to 5, 7, a to d pnfsan=1 0.1v dd v continued on next page.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-18/32 continued from preceding page. specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit pin capacitance cp all pins ? for pins other than that under test: v in =v ss ? f=1mhz ? ta=25c 10 pf vdet(1) v dd cpu on low voltage detection circuit excluding the hold mode 2.7 2.85 3.0 v low voltage circuit detection voltage vdet(2) v dd cpu on low voltage detection circuit hold mode 1.27 1.42 1.57 v serial i/o characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v 1. sio0, sio1 serial i/o characterist ics (wakeup function disabled) (note 4-1-1) specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit period tsck(1) 4 low level pulse width tsckl(1) 2 tsckh(1) ? see fig. 1. 2 tsckha(1) ? automatic communication mode ? see fig. 1. 6 tsckhbsy (1a) ? automatic communication mode ? see fig. 1. 23 input clock high level pulse width tsckhbsy (1b) sck0(p12) sck1(p45) ? modes other than automatic communication mode ? see fig. 1. v dd port= v dd (1) to 5.5 4 period tsck(2) 4 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 1. 1/2 tsck tsckha(2) ? automatic communication mode ? cmos output selected ? see fig. 1. 6 tsckhbsy (2a) ? automatic communication mode ? cmos output selected ? see fig. 1. 4 23 serial clock output clock high level pulse width tsckhbsy (2b) sck0(p12) sck1(p45) ? modes other than automatic communication mode ? see fig. 1. v dd port= v dd (1) to 5.5 4 tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) sio0(p11), sio1(p44) ? specified with respect to rising edge of sioclk ? see fig. 1. v dd port= v dd (1) to 5.5 0.03 input clock tdd0(1) ? (note 4-1-2) 1tcyc +0.05 serial output output clock output delay time tdd0(2) so0(p10), so1(p43), sio0(p11), sio1(p44) ? (note 4-1-2) v dd port= v dd (1) to 5.5 1tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: specified with respect to falling edge of sioc lk. specified as the time to the beginning of output state change in open drain output mode. see fig. 1.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-19/32 2. sio0, sio1 serial input/output characteris tics (wakeup function enabled) (note 4-2-1) specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit period tsck(3) 2 low level pulse width tsckl(3) 1 tsckh(3) 1 serial clock input clock high level pulse width tsckhbsy(3) sck0(p12) sck1(p45) ? see fig. 1. v dd port= v dd (1) to 5.5 2 tcyc data setup time tsdi(2) 0.03 serial input data hold time thdi(2) sio0(p11), sio1(p44) ? specified with respect to rising edge of sioclk ? see fig. 1. v dd port= v dd (1) to 5.5 0.03 serial output input clock output delay time tdd0(3) so0(p10), so1(p43), sio0(p11), sio1(p44) ? (note 4-2-2) v dd port= v dd (1) to 5.5 1tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. note 4-2-2: specified with respect to falling edge of sioc lk. specified as the time to the beginning of output state change in open drain output mode. see fig. 1. 3. smiic0 to smiic3 simple sio m ode input/output characteristics specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit period tsck(4) 4 low level pulse width tsckl(4) 2 input clock high level pulse width tsckh(4) sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) ? see fig. 1. v dd port= v dd (1) to 5.5 2 period tsck(5) 8 tcyc low level pulse width tsckl(5) 1/2 serial clock output clock high level pulse width tsckh(5) sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) ? cmos output selected ? see fig. 1. v dd port= v dd (1) to 5.5 1/2 tsck data setup time tsdi(3) 0.03 serial input data hold time thdi(3) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? specified with respect to rising edge of sioclk ? see fig. 1. v dd port= v dd (1) to 5.5 0.03 serial output output delay time tdd0(4) sm0do(p24) sm0d1(pa2) sm0d2(pa5) sm0d3(p77) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? specified with respect to falling edge of sioclk ? specified as interval up to time when output state starts changing. ? see fig. 1. v dd port= v dd (1) to 5.5 1tcyc +0.05 s note 4-5-1: these specifications are theoretical values. add margin depending on its use.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-20/32 * remarks: dix and dox denote the last bits communicated; x = 0 to 32768 figure 1 serial i/o waveforms dataout: dataout: dataout: data transfer period (sio0 and sio1 only) data transfer period (sio0 and sio1 only) di0 di7 dix di8 do0 do7 dox do8 di1 do1 sioclk: datain: datain: datain: sioclk: tsck tsckl tsckh thdi tsdi tsckl tsckha thdi tsdi tddo tsckhbsy run: di6 do6 tsckhbsy sioclk:
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-21/32 4. smiic0 to smiic3 i 2 c mode input/output characteristics specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit period tscl 5 low level pulse width tscll 2.5 input clock high level pulse width tsclh sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) ? see fig. 2. v dd port= v dd (1) to 5.5 2 period tsclx 10 tfilt low level pulse width tscllx 1/2 serial clock output clock high level pulse width tsclhx sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) ? specified as interval up to time when output state starts changing. v dd port= v dd (1) to 5.5 1/2 tscl sm0c and sm0da pins input spike suppression time tsp sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? see fig. 2. 1 tfilt input tbuf ? see fig. 2. 2.5 ? standard-mode ? specified as interval up to time when output state starts changing. 5.5 bus release time between start and stop output tbufx sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? fast-mode ? specified as interval up to time when output state starts changing. v dd port= v dd (1) to 5.5 1.6 s ? when smiic register control bit, i2cshds=0 ? see fig. 2. 2.0 input thd; sta ? when smiic register control bit, i2cshds=1 ? see fig. 2. 2.5 tfilt ? standard-mode ? specified as interval up to time when output state starts changing. 4.1 start/restart condition hold time output thd; stax sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? fast-mode ? specified as interval up to time when output state starts changing. v dd port= v dd (1) to 5.5 1.0 s input tsu; sta ? see fig. 2. 1.0 tfilt ? standard-mode ? specified as interval up to time when output state starts changing. 5.5 restart condition setup time output tsu; stax sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? fast-mode ? specified as interval up to time when output state starts changing. v dd port= v dd (1) to 5.5 1.6 s input tsu; sto ? see fig. 2. 1.0 tfilt ? standard-mode ? specified as interval up to time when output state starts changing. 4.9 stop condition setup time output tsu; stox sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? fast-mode ? specified as interval up to time when output state starts changing. v dd port= v dd (1) to 5.5 1.1 s note 4-6-1: these specifications are theoretical values. add margin depending on its use. continued on next page.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-22/32 continued from preceding page. specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit input thd; dat ? see fig. 2. 0 data hold time output thd; datx sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? specified as interval up to time when output state starts changing. v dd port= v dd (1) to 5.5 1 1.5 tfilt input tsu; dat ? see fig. 2. 1 data setup time output tsu; datx sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? specified as interval up to time when output state starts changing. v dd port= v dd (1) to 5.5 1tscl -1.5tfilt tfilt input tf ? see fig. 2. v dd port= v dd (1) to 5.5 300 ? when smiic register control bits, pslw=1, p5v=1 v dd port=5 20+0.1cb 250 ? when smiic register control bits, pslw=1, p5v=0 v dd port=3 20+0.1cb 250 fall time output tf sm0ck(p22) sm1ck(pa0) sm2ck(pa3) sm3ck(p75) sm0da(p23) sm1da(pa1) sm2da(pa4) sm3da(p76) ? when smiic register control bits, pslw=0 ? cb 400pf v dd port= v dd (1) to 5.5 100 ns note 4-6-1: these specifications are theoretical values. add margin depending on its use. note 4-6-2: the value of tfilt is determined by the values of the register smicnbrg (n=0, 1, 2, 3), bits 7 and 6 (brp1, brp0) and the system clock frequency. brp1 brp0 tfilt 0 0 tcyc 1 0 1 tcyc 2 1 0 tcyc 3 1 1 tcyc 4 set bits (bpr1, bpr0) so that the value of tfilt falls between the following range: 250ns tfilt > 140ns note 4-6-3: cb represents the total loads (in pf) connected to the bus pins. cb 400pf note 4-6-4: the standard-mode refers to a mode that is entered by configuring smicnbrg (n=0, 1, 2, 3) as follows: 250ns tfilt > 140ns brdq (bit5) = 1 scl frequency setting 100khz the fast-mode refers to a mode that is entered by configuring smicnbrg (n=0, 1, 2, 3) as follows: 250ns tfilt > 140ns brdq (bit5) = 0 scl frequency setting 400khz
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-23/32 tbuf thd;sta tlow tr thd;dat thigh tf tsu;dat tsu;sta thd;sta tsp tsu;sto p s sr p sda sck s: start condition p: stop condition sr: restart condition figure 2 i 2 c timing 5. uart2 to uart5 operating conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit transfer rate ubr u2rx(p16), u3rx(p34), u4rx(pd0), u5rx(pa6), u2tx(p17), u3tx(p35), u4tx(pd1), u5tx(pa7) v dd port= v dd (1) to 5.5 8 4096 tbgcyc note 4-7: tbgcyc denotes one cy cle of the baudrate clock source. pulse input conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p30), int1(p31), int2(p32), int3(p33), int4(p20), int5(p21), int6(p40), int7(pb5) ? interrupt source flag can be set. ? event inputs for timers 2 and 3 are enabled. v dd port= v dd (1) to 5.5 2 tcyc tpil(2) resb can be reset via the external reset pin. (note 5-1) v dd cpu= 3.0 to 3.6 50 s high/low level minimum pulse width tpil(3) v dd cpu can be reset by the low voltage detection circuit. (note 5-1) (note 5-2) 50 s note 5-1: this parameter specifies the time required to en sure that the reset sequence is carried out without fail. the reset may be applied even if this time specification is not satisfied. note 5-2: (v dd cpu voltage) (low voltage circuit detection voltage) figure 3 pulse input timing signal waveform tpil tpih
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-24/32 ad converter characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v 1. 12-bit ad conversion mode specification parameter symbol applicable pin /remarks conditions v dd cpu[v] min typ max unit resolution nad 3.0 to 3.6 12 bit absolute accuracy etad (note 6-1) 3.0 to 3.6 16 lsb conversion time tcad12 conversion time calculated 3.0 to 3.6 102 s analog input voltage range vain 3.0 to 3.6 v ss v dd cpu v iainh vain=v dd cpu 3.0 to 3.6 1 analog port input current iainl an0(p60) to an7(p67), an8(p70) to an12(p74) vain=v ss 3.0 to 3.6 -1 a conversion time calculation formula: tcad12= ((52/( ad division ratio))+2) tcyc 2. 8-bit ad conversion mode specification parameter symbol applicable pin /remarks conditions v dd cpu[v] min typ max unit resolution nad 3.0 to 3.6 8 bit absolute accuracy etad (note 6-1) 3.0 to 3.6 1.5 lsb conversion time tcad8 conversion time calculated 3.0 to 3.6 32 s analog input voltage range vain 3.0 to 3.6 v ss v dd cpu v iainh vain=v dd cpu 3.0 to 3.6 1 analog port input current iainl an0(p60) to an7(p67), an8(p70) to an12(p74) vain=v ss 3.0 to 3.6 -1 a conversion time calculation formula: tcad8= ((32/(ad division ratio))+2) tcyc note 6-1: the quantization error ( 1/2lsb) is excluded fro m the absolute accuracy. note 6-2: the conversion time refers to the interval from th e time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. the conversion time is twice the normal value when one of the following conditions occurs: ? the first ad conversion is executed in the 12 -bit ad conversion mode after a system reset. ? the first ad conversion is executed after the ad conversion mode is switched from 8-bit to 12-bit ad conversion mode.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-25/32 consumption current characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit iddop(1) ? fmx?tal =32.768khz crystal oscillation mode ? system clock set to vco (12mhz) ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 3.6 10 15 iddop(2) ? fmx?tal =32.768khz crystal oscillation mode ? system clock set to vco (8mhz) ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 3.6 8 12 iddop(3) ? fmx?tal =32.768khz crystal oscillation mode ? system clock set to vco (4mhz) ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 3.6 6 9 iddop(4) ? fmx?tal=0khz (oscillation stopped) ? system clock set to internal rc oscillation ? 1/1 frequency division mode 3.0 to 3.6 3.5 5 ma normal mode consumption current (note 7-1) iddop(5) v dd cpu =v dd port1 =v dd port2 =v dd pll ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 3.6 35 150 a iddhalt(1) halt mode ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to vco (12mhz) ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 3.6 3.5 5 iddhalt(2) halt mode ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to vco (8mhz) ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 3.6 2.5 4 iddhalt(3) halt mode ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to vco (4mhz) ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 3.6 1.5 3 iddhalt(4) halt mode ? fmx?tal=0khz (oscillation stopped) ? system clock set to internal rc oscillation ? 1/1 frequency division mode 3.0 to 3.6 0.2 1 ma halt mode consumption current (note 7-1) iddhalt(5) v dd cpu =v dd port1 =v dd port2 =v dd pll halt mode ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 3.6 15 100 hold mode consumption current iddhold(1) v dd cpu hold mode 3.0 to 3.6 1 30 holdx mode consumption current iddhold(2) v dd cpu holdx mode ? fmx?tal=32.768khz crystal oscillation mode 3.0 to 3.6 15 50 a note 7-1: the consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors.
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-26/32 f-rom programming characteristics at ta = +10 c to +55 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin /remarks conditions v dd cpu[v] min typ max unit onboard programming current i dd fw(1) v dd cpu ? microcontroller erase consumption current is excluded. 3.0 to 3.6 10 20 ma tfw(1) ? 512-byte erase operation 3.0 to 3.6 20 30 ms onboard programming time tfw(2) ? 2-byte programming operation 3.0 to 3.6 40 60 s
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-27/32 power pin treatment condition 1 (v dd cpu, v ss 1) connect capacitors that meet the following conditions between the v dd 1 and v ss 1 pins: ? connect among the v dd cpu and v ss 1 pins and the capacitors c1 and c2 with the shortest possible lead wires, of the same length (l1=l1?, l2=l2?) wherever possible. ? connect a large-capacity cap acitor c1 and a small-capacity capacitor c2 in parallel. ? the capacitance of c2 should be approximately 0.1 f or larger. ? please mount a suitable capacitor about c1. ? the v dd cpu and v ss 1 traces must be thicker than the other traces. figure 4 power pin treatment condition 2 (v dd port1 to 2, v ss 2 to 3) connect capacitors that meet the following conditions between the v dd port1 to v ss 2 and v dd port2 to v ss 3 pins: ? connect among the v dd port1 to 2 and v ss 2 to 3 pins and the capacitor c3 with the shortest possible lead wires, of the same length (l3=l3?) wherever possible. ? the capacitance of c3 should be approximately 0.1 f or larger. ? the v dd port1 to 2 and v ss 2 to 3 traces must be thicker than the other traces. figure 5 v dd cpu v ss 1 l1? l2? l1 l2 c1 c2 v dd port1/ v dd port2 v ss 2/ v ss 3 l3? l3 c3
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-28/32 power pin treatment condition 3 (v dd pll, v ss 4) connect capacitors that meet the following conditions between the v dd pll and v ss 4 pins: ? connect among the v dd pll and v ss 4 pins and the capacitors c4 and c5 with the shortest possible lead wires, of the same length (l4=l4?, l5=l5?) wherever possible. ? connect a large-capacity cap acitor c4 and a small-capacity capacitor c5 in parallel. ? the capacitance of c4 should be approximately 10 f. ? the capacitance of c5 should be approximately 0.1 f. ? the v dd pll and v ss 4 traces must be thicker than the other traces. figure 6 power pin treatment condition 4 (vreg, v ss 1) connect capacitors that meet the following conditions between the vreg and v ss 1 pins: ? connect among the vreg and v ss 1 pins and the capacitors c6 with the shortest possible lead wires, of the same length (l6=l6?) wherever possible. ? the capacitance of c6 should be approximately 1 f. ? the vreg and v ss 1 traces must be thicker than the other traces. figure 7 v dd pll v ss 4 l4? l5? l4 l5 c4 c5 vreg v ss 1 l6? l6 c6
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-29/32 lpf pin treatment condition (lpfo) insert a resistor and capacitors that meet th e following conditions between the lpfo and v ss 4 pins. r1 = 3.3k c7 = 0.068 f c8 = 0.0039 f ? routing traces between the lpfo and v ss 4 pins and the resistor and capacitors, and between r1 and c7 must be as short as possible. * after the pll circuit is activated, 50ms or more is required for stabilizing oscillation. figure 8 test pin treatment condition (test) insert a resistor that meets the follo wing condition between the test and v ss 1 pins. r test = 100k figure 9 lpfo v ss 4 c8 c7 r1 test v ss 1 r test
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-30/32 example of crystal oscillator circuit characteristics given below are the characteristics of a sa mple crystal oscillator circuit that were measured using a sanyo-designated oscillation characteristics evaluation boar d and external components with circu it constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 example of crystal oscillator circu it characteristics with a crystal resonator circuit constant nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rd [ ] operating voltage range [v] oscillator stabilization time tms x'tal (typ) [s] remarks 32.768khz river eletec tfx-03 (cl=12.5pf) 15 15 680k v dd cpu= 3.0 to 3.6 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the xt oscillator circuit is executed plus the time interval that is required for the oscillation to g et stabilized after the hold mode is released (see figure 11). note: the traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern. figure 10 xt oscillator circuit c1 rd c2 x?tal xt2 xt1
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau no.a1853-31/32 figure 11 reset time and oscillation stabilization time *1: the voltage when the power is turned on and off must stand in the following relationship: v dd port v dd cpu. it should be noted that, while the v dd port power is supplied, the i/o pin remains in an undefined state until the v dd cpu voltage reaches the a llowable operation range. figure 12 hold release and oscillation stabilization time operating v dd lower limit tms x't a l v dd cpu 0v reset time tpil(2) power v dd cpu resb internal rc oscillation xt1, xt2 operating mode unpredictable reset i n iti a li za ti on i ns t ruc ti on execution user instruction execution power v dd port *1 tms x't a l internal rc oscillation xt1, xt2 state hold halt instruction execution hold release no hold release signal hold release signal valid interrupt operation
lc88f40h0pa/h0pau/f0pa/f0pau/d0pa/d0pau ps no.a1853-32/32 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. reset pin treatment condition (resb) (note) when the power is turned on, the resb pin must be set to the low level. (a reset period of 50 s or longer is required after the power has stabilized.) recommended value r res : 100k c res : 0.033 f figure 13 reset circuit this catalog provides information as of december, 2010. specifications and inform ation herein are subject to change without notice. c res v dd cpu r res resb

▲Up To Search▲

Price & Availability of LC88F40F0PAU

	To Download LC88F40F0PAU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .